***********************************************************
*
* PRTR5V0U1T
*
* Nexperia
*
* Ultra low capacitance single rail-to-rail ESD protection
* VRWM     = 5,5V
* CI/O-GND = 1,5pF @ f = 1MHz, VI/O-GND = 0V
* IR       = 100nA @ VR = 3V
* 
* 
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT23
* 
* Package Pin 1: I/O  Input
* Package Pin 2: Supply Voltage
* Package Pin 3: Ground
*
*
* Extraction date (week/year): #
* Simulator: SPICE2
*
***********************************************************
*
.SUBCKT  PRTR5V0U1T 1 2 3
DZ 3 2 DZ
D1 1 2 DO
D2 3 1 DU
*
.Model DZ D
+ CJO=15.7E-12
+ VJ=.624
+ M=.274
+ BV = 7.3
*
.Model DO D
+ CJO=0.37E-12
+ VJ=.65
+ M=.36
+ BV = 50
*
.Model DU D
+ CJO=0.37E-12
+ VJ=.778
+ M=.36
+ BV = 50
*
.ENDS
*