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*
* PBSS5230PAP
*
* Nexperia
*
* Double Low VCEsat PNP/PNP Transistor
* IC   = 2 A
* VCEO = 30 V 
* hFE  = typ. 290  @ 2V/500mA
*
* 
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 1118
* 
* Package Pin 1/4: Emitter   TR1/TR2
* Package Pin 2/5: Base      TR1/TR2
* Package Pin 6/3: Collector TR1/TR2
* Package Pin 8/7: Collector TR1/TR2
*
* Extraction date (week/year): 43/2012
* Spicemodel does not include temperature dependency
*
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*#
* Please note: The following model is to be used twice in 
* schematic due to equality of both Transistors.
*
* Diode D1 is dedicated to improve modeling in reverse
* mode of operation and does not reflect a physical device.
*
.SUBCKT PBSS5230PAP 1 2 3
Q1 1 2 3 MAIN 
D1 1 2 DIODE 
*
.MODEL MAIN PNP
+ IS = 2.531E-013
+ NF = 0.9846
+ ISE = 8.69E-015
+ NE = 1.313
+ BF = 413.3
+ IKF = 0.9036
+ VAF = 18.62
+ NR = 0.9843
+ ISC = 5.395E-012
+ NC = 2.965
+ BR = 100
+ IKR = 0.2891
+ VAR = 10.19
+ RB = 28
+ IRB = 0.001
+ RBM = 0.66
+ RE = 0.06321
+ RC = 0.05746
+ XTB = 0
+ EG = 1.11
+ XTI = 3
+ CJE = 1.529E-010
+ VJE = 0.8233
+ MJE = 0.4091
+ TF = 2.529E-009
+ XTF = 17.8
+ VTF = 1.1
+ ITF = 1.35
+ PTF = 0
+ CJC = 6.949E-011
+ VJC = 0.5616
+ MJC = 0.3803
+ XCJC = 1
+ TR = 3.5E-009
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.8
.MODEL DIODE D
+ IS = 2.004E-014
+ N = 1.137
+ BV = 1000
+ IBV = 0.001
+ RS = 9638
+ CJO = 0
+ VJ = 1
+ M = 0.7
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
*