********************************************************** * * PBSS5160PAPS * * Nexperia * * 2 low VCEsat PNP transistors * IC = 1 A * VCEO = 60 V * hFE = typ. 170 @ 2V/500mA * * * * Package pinning does not match Spice model pinning. * Package: SOT 1118 * * Package Pin 1/4: Emitter TR1/TR2 * Package Pin 2/5: Base TR1/TR2 * Package Pin 6/3: Collector TR1/TR2 * Package Pin 8/7: Collector TR1/TR2 * * * Extraction date (week/year): 43/2012 * Spicemodel does not include temperature dependency * ********************************************************** *# * Please note: The following model is to be used twice in * schematic due to equality of both transistors. * * Diode D1, Transistor Q2 and resistor RQ * are dedicated to improve modeling of quasi * saturation area and reverse mode operation * and do not reflect physical devices. * .SUBCKT PBSS5160PAPS 1 2 3 Q1 1 2 3 MAIN 0.6756 Q2 11 2 3 MAIN 0.3244 RQ 1 11 5.542 D1 1 2 DIODE * .MODEL MAIN PNP + IS = 1.098E-013 + NF = 0.9878 + ISE = 1.569E-014 + NE = 1.42 + BF = 280 + IKF = 0.5126 + VAF = 36.99 + NR = 0.9871 + ISC = 8.551E-014 + NC = 1.789 + BR = 24 + IKR = 0.4 + VAR = 18 + RB = 20 + IRB = 0.001 + RBM = 1 + RE = 0.06321 + RC = 0.04181 + XTB = 0 + EG = 1.11 + XTI = 3 + CJE = 9.789E-011 + VJE = 0.7587 + MJE = 0.3741 + TF = 1.773E-009 + XTF = 20 + VTF = 1.1 + ITF = 1.35 + PTF = 0 + CJC = 3.162E-011 + VJC = 0.7543 + MJC = 0.4479 + XCJC = 1 + TR = 3E-008 + CJS = 0 + VJS = 0.75 + MJS = 0.333 + FC = 0.7544 .MODEL DIODE D + IS = 1.409E-014 + N = 1.079 + BV = 1000 + IBV = 0.001 + RS = 1524 + CJO = 0 + VJ = 1 + M = 0.7 + FC = 0 + TT = 0 + EG = 1.11 + XTI = 3 .ENDS *