*********************************************************** * * PBSS5130PAP * * Nexperia * * Double Low VCEsat PNP/PNP Transistor * IC = 1 A * VCEO = 30 V * hFE = typ. 250 @ 2V/500mA * * * * * Package pinning does not match Spice model pinning. * Package: SOT 1118 * * Package Pin 1/4: Emitter TR1/TR2 * Package Pin 2/5: Base TR1/TR2 * Package Pin 6/3: Collector TR1/TR2 * Package Pin 8/7: Collector TR1/TR2 * * Extraction date (week/year): 43/2012 * Spicemodel does not include temperature dependency * ********************************************************** *# * Please note: The following model is to be used twice in * schematic due to equality of both Transistors. * .SUBCKT PBSS5130PAP 1 2 3 Q1 1 2 3 MAIN * .MODEL MAIN PNP + IS = 1.536E-013 + NF = 0.9892 + ISE = 5.47E-015 + NE = 1.276 + BF = 387.5 + IKF = 0.5111 + VAF = 22.33 + NR = 0.9885 + ISC = 8.222E-015 + NC = 1.119 + BR = 80 + IKR = 0.824 + VAR = 19.93 + RB = 22 + IRB = 0.001 + RBM = 1.24 + RE = 0.06321 + RC = 0.06916 + XTB = 0 + EG = 1.11 + XTI = 3 + CJE = 9.466E-011 + VJE = 0.8044 + MJE = 0.3919 + TF = 1.762E-009 + XTF = 20 + VTF = 1.1 + ITF = 1.35 + PTF = 0 + CJC = 3.162E-011 + VJC = 1 + MJC = 0.3398 + XCJC = 1 + TR = 6E-009 + CJS = 0 + VJS = 0.75 + MJS = 0.333 + FC = 0.8 .ENDS *