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*
* PBSS5112PAP
*
* Nexperia
*
* Double Low VCEsat PNP/PNP Transistor
* IC   = 1 A
* VCEO = 120 V 
* hFE  = typ. 85  @ 2V/500mA
*
* 
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 1118
* 
* Package Pin 1/4: Emitter   TR1/TR2
* Package Pin 2/5: Base      TR1/TR2
* Package Pin 6/3: Collector TR1/TR2
* Package Pin 8/7: Collector TR1/TR2
*
* Extraction date (week/year): 43/2012
* Spicemodel does not include temperature dependency
*
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*#
* Please note: The following model is to be used twice in 
* schematic due to equality of both Transistors.
*
* Diode D1, Transistor Q2 and Resistor RQ 
* are dedicated to improve modeling of quasi
* saturation area and reverse mode operation
* and do not reflect physical devices.
*
.SUBCKT PBSS5112PAP 1 2 3
Q1 1 2 3 MAIN 0.5962
Q2 11 2 3 MAIN 0.4038
RQ 1 11 18.97
D1 1 2 DIODE
*
.MODEL MAIN PNP
+ IS = 2.324E-013
+ NF = 0.9881
+ ISE = 2.871E-014
+ NE = 1.295
+ BF = 368
+ IKF = 0.7586
+ VAF = 37.07
+ NR = 0.9872
+ ISC = 1.541E-013
+ NC = 1.821
+ BR = 11.91
+ IKR = 2.051
+ VAR = 18
+ RB = 25
+ IRB = 0.000462
+ RBM = 0.7
+ RE = 0.07254
+ RC = 0.01
+ XTB = 0
+ EG = 1.11
+ XTI = 3
+ CJE = 1.46E-010
+ VJE = 0.7663
+ MJE = 0.3897
+ TF = 2.179E-009
+ XTF = 20
+ VTF = 1.1
+ ITF = 1.35
+ PTF = 0
+ CJC = 3.6E-011
+ VJC = 0.7757
+ MJC = 0.4771
+ XCJC = 1
+ TR = 2.7E-008
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.8
.MODEL DIODE D
+ IS = 1.466E-013
+ N = 1.03
+ BV = 1000
+ IBV = 0.001
+ RS = 549.5
+ CJO = 0
+ VJ = 1
+ M = 0.7
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
*