********************************************************** * * PBSS4350SS * * Nexperia * * Low VCEsat double NPN/NPN (BISS) Transistor * IC = 2.7 A * VCEO = 50 V * hFE = typ. 520 @ 2V/100mA * * * * * Package pinning does not match Spice model pinning. * Package: SOT 96 * * Package Pin 1;3: Emitter TR1;TR2 * Package Pin 2;4: Base TR1;TR2 * Package Pin 5;6;7;8: Collector TR2;TR2;TR1;TR1 * * * Extraction date (week/year): 27/2019 * Spicemodel includes temperature dependency * ********************************************************** *# * Please note: The following model is to be used twice in * schematic due to equality of both Transistors. * * Diode D1, Transistor Q2 and resistor RQ * are dedicated to improve modeling of quasi * saturation area and reverse mode operation * and do not reflect physical devices. * .SUBCKT PBSS4350SS 1 2 3 Q1 1 2 3 MAIN 0.7673 Q2 11 2 3 MAIN 0.2327 RQ 1 11 3.827 D1 2 1 Diode * .MODEL MAIN NPN + IS = 7.804E-13 + NF = 0.9729 + ISE = 1.66E-13 + NE = 1.339 + BF = 440 + IKF = 2.529 + VAF = 46.42 + NR = 0.9736 + ISC = 2.042E-13 + NC = 1.416 + BR = 106.6 + IKR = 3.486 + VAR = 48.81 + RB = 14 + IRB = 0.0007 + RBM = 5 + RE = 0.1029 + RC = 0.01148 + XTB = 2.491 + EG = 1.11 + XTI = 6.622 + CJE = 3.197E-10 + VJE = 0.7416 + MJE = 0.3668 + TF = 6.8E-10 + XTF = 4.988 + VTF = 2.368 + ITF = 1.121 + PTF = 0 + CJC = 5.972E-11 + VJC = 0.6592 + MJC = 0.438 + XCJC = 1 + TR = 5.5E-08 + CJS = 0 + VJS = 0.75 + MJS = 0.333 + FC = 0.7908 .MODEL DIODE D + IS = 2.612E-14 + N = 1.035 + BV = 1000 + IBV = 0.001 + RS = 2350 + CJO = 0 + VJ = 1 + M = 0.5 + FC = 0 + TT = 0 + EG = 1.11 + XTI = 3 .ENDS *