**********************************************************
*
* PBSS4260PANS
*
* Nexperia
*
* Low VCEsat (BISS) double NPN/NPN transistors
* VCEO = 60 V
* IC   = 2 A 
* hFE  = typ. 400 @ 2V/100mA  
* 
*
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 1118D
*
* Package Pin 1 (4): Emitter   TR1 (TR2)
* Package Pin 2 (5): Base      TR1 (TR2)
* Package Pin 6 (3): Collector TR1 (TR2)
* Package Pin 7 (8): Collector TR1 (TR2)
*
* Extraction date (week/year): 48/2021 
* Spice model includes temperature dependency
*
**********************************************************
*#
* Please note: The following model is to be used twice in 
* schematic due to equality of both transistors.
*
* Diode D1, Transistor Q2 and Resistor RQ 
* are dedicated to improve modeling of quasi
* saturation area and reverse mode operation
* and do not reflect physical devices.
* 
.SUBCKT PBSS4260PANS 1 2 3
Q1 1 2 3 MAIN 0.8741
Q2 11 2 3 MAIN 0.1259
RQ 1 11 26.32
D1 2 1 DIODE
*
.MODEL MAIN NPN
+ IS = 2.952E-13
+ NF = 0.9735
+ ISE = 2.78E-15
+ NE = 1.253
+ BF = 443
+ IKF = 0.8266
+ VAF = 19.97
+ NR = 0.9736
+ ISC = 9.385E-14
+ NC = 1.415
+ BR = 101.4
+ IKR = 4.198
+ VAR = 20.14
+ RB = 80
+ IRB = 0.0004
+ RBM = 7.5
+ RE = 0.05685
+ RC = 0.03986
+ XTB = 1.45
+ EG = 1.11
+ XTI = 10.73
+ CJE = 1.606E-10
+ VJE = 0.8756
+ MJE = 0.4847
+ TF = 1.4E-09
+ XTF = 18
+ VTF = 1.5
+ ITF = 0.7
+ PTF = 0
+ CJC = 1.862E-11
+ VJC = 0.4
+ MJC = 0.2859
+ XCJC = 1
+ TR = 2.1E-08
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.9
.MODEL DIODE D
+ IS = 1.258E-13
+ N = 1.055
+ BV = 1000
+ IBV = 0.001
+ RS = 380.3
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
*