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*
* PBSS4260PAN
*
* Nexperia
*
* Low VCEsat (BISS) double NPN/NPN transistor
* IC   = 2 A
* VCEO = 60 V 
* hFE  = typ. 430  @ 2V/100mA
*
* 
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 1118
* 
* Package Pin 1/4: Emitter   TR1/TR2
* Package Pin 2/5: Base      TR1/TR2
* Package Pin 6/3: Collector TR1/TR2
* Package Pin 7/8: Collector TR1/TR2
*
* Extraction date (week/year): 48/2021
* Spicemodel includes temperature dependency
*
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*#
* Please note: The following model is to be used twice in 
* schematic due to equality of both transistors.
*
* Diode D1, Transistor Q2 and Resistor RQ 
* are dedicated to improve modeling of quasi
* saturation area and reverse mode operation
* and do not reflect physical devices.
*
.SUBCKT PBSS4260PAN 1 2 3
Q1 1 2 3 MAIN 0.9
Q2 11 2 3 MAIN 0.1
RQ 1 11 23.35
D1 2 1 DIODE
*
.MODEL MAIN NPN
+ IS = 1.999E-13
+ NF = 0.9559
+ ISE = 4.836E-13
+ NE = 2.5
+ BF = 456.2
+ IKF = 0.6453
+ VAF = 19.34
+ NR = 0.9562
+ ISC = 6.153E-14
+ NC = 1.137
+ BR = 74.95
+ IKR = 20.14
+ VAR = 42.36
+ RB = 40
+ IRB = 0.0008
+ RBM = 1.6
+ RE = 0.04503
+ RC = 0.02901
+ XTB = 1.309
+ EG = 1.11
+ XTI = 12.09
+ CJE = 1.54E-10
+ VJE = 0.8769
+ MJE = 0.4834
+ TF = 1.005E-09
+ XTF = 12.44
+ VTF = 1.5
+ ITF = 0.4216
+ PTF = 0
+ CJC = 1.974E-11
+ VJC = 0.4
+ MJC = 0.2924
+ XCJC = 1
+ TR = 3.3E-08
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.9
.MODEL DIODE D
+ IS = 4.393E-15
+ N = 0.8872
+ BV = 1000
+ IBV = 0.001
+ RS = 1459
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
*