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*
* PBSS4130PAN
*
* Nexperia
*
* Double Low VCEsat NPN/NPN Transistor
* IC   = 1 A
* VCEO = 30 V 
* hFE  = typ. 320  @ 2V/500mA
*
* 
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 1118
* 
* Package Pin 1/4: Emitter   TR1/TR2
* Package Pin 2/5: Base      TR1/TR2
* Package Pin 6/3: Collector TR1/TR2
* Package Pin 8/7: Collector TR1/TR2
*
* Extraction date (week/year): 43/2012
* Spicemodel does not include temperature dependency
*
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*#
* Please note: The following model is to be used twice in 
* schematic due to equality of both Transistors.
*
* Diode D1 is dedicated to improve modeling in reverse
* mode of operation and does not reflect a physical device.
*
.SUBCKT PBSS4130PAN 1 2 3 
Q1 1 2 3 MAIN 
D1 2 1 DIODE 
*
.MODEL MAIN NPN
+ IS = 8.732E-014
+ NF = 0.9718
+ ISE = 4.178E-015
+ NE = 1.387
+ BF = 433
+ IKF = 1.618
+ VAF = 48.86
+ NR = 0.9721
+ ISC = 5.953E-016
+ NC = 1.037
+ BR = 175.8
+ IKR = 1.101
+ VAR = 39
+ RB = 26
+ IRB = 0.0009
+ RBM = 1.7
+ RE = 0.05746
+ RC = 0.07413
+ XTB = 0
+ EG = 1.11
+ XTI = 3
+ CJE = 1.135E-010
+ VJE = 0.66
+ MJE = 0.3208
+ TF = 1.054E-009
+ XTF = 13.16
+ VTF = 25
+ ITF = 3.093
+ PTF = 0
+ CJC = 2.066E-011
+ VJC = 0.1327
+ MJC = 0.2016
+ XCJC = 1
+ TR = 8E-009
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.8177
.MODEL DIODE D
+ IS = 2.082E-015
+ N = 0.9929
+ BV = 1000
+ IBV = 0.001
+ RS = 857.2
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
*