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*
* PBSS4021SP
*
* Nexperia
*
* Low VCEsat PNP (BISS) double PNP/PNP Transistor
* IC   = 6,3 A
* VCEO = 20 V
* hFE  = typ. 550 @ 2V/500mA
* 
*
* 
*
* Package pinning does not match Spice model pinning.
* Package: SOT 96-1
*
* Package Pin 1;5: Emitter;Collector
* Package Pin 2;6: Base;Collector
* Package Pin 3;7: Emitter;Collector
* Package Pin 4;8: Base;Collector
*
* Extraction date (week/year): 08/2018
* Spicemodel includes temperature dependency
*
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*#
* Please note: The following model is to be used twice in 
* schematic due to equality of both Transistors.
*
* Diode D1 is dedicated to improve modeling in reverse
* mode of operation and does not reflect a physical device.
*
.SUBCKT PBSS4021SP 1 2 3
Q1 1 2 3 MAIN
D1 1 2 DIODE
*
.MODEL MAIN PNP
+ IS = 2.564E-012
+ NF = 0.9892
+ ISE = 3.076E-013
+ NE = 1.356
+ BF = 411.2
+ IKF = 4.528
+ VAF = 27.3
+ NR = 0.9899
+ ISC = 2.002E-014
+ NC = 1.056
+ BR = 173.6
+ IKR = 2.64
+ VAR = 12.69
+ RB = 13.5
+ IRB = 0.001
+ RBM = 2.2
+ RE = 0.0182
+ RC = 0.009262
+ XTB = 1.804
+ EG = 1.11
+ XTI = 8.231
+ CJE = 8.619E-010
+ VJE = 0.7893
+ MJE = 0.3914
+ TF = 2.5E-009
+ XTF = 2
+ VTF = 5
+ ITF = 2
+ PTF = 0
+ CJC = 2.627E-010
+ VJC = 0.3816
+ MJC = 0.2806
+ XCJC = 1
+ TR = 1.3E-009
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.9
.MODEL DIODE D
+ IS = 3.939E-013
+ N = 1.138
+ BV = 1000
+ IBV = 0.001
+ RS = 1159
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
*